This invention pertains to semiconductor device which make use of metallic silicides to form a layer serving as an electrode or as a wire, and it further pertains to a process of fabricating such semiconductor devices. More particularly, this is an invention in technology for the adhesion promotion between a metallic silicide film and an overlaying dielectric layer.
Generally, in semiconductor devices of very large scale integration (VLSI), their operating speed much depends on the resistivity of a material of a wire used to transmit a signal from one circuit component to the other. Accordingly, it is most desired that wiring material, which serves as transistor electrode or as a direct intrachip connection, is a low-resistivity material. For this reason, metallic silicides are an attractive wiring material, having a low resistivity as compared to polycrystalline silicon (polysilicon). The effect of using metallic silicides gives a further advantage that the cost of forming wiring layers can be kept low, compared to multilayering metal layers. Metallic silicides have been used increasingly as wiring materials in the semiconductor manufacturers.
Various metallic silicides, which melt at high temperatures, are known, some of which are molybdenum silicide (MoSix), titanium silicide (TiSix), and tungsten silicide (WSix). These metallic silicides have a lower resistivity than polysilicon, and the use of metallic silicides makes the process of forming a wiring layer easier. However, metallic silicides are likely to be oxidized. Further, metallic components of silicides (for example, tungsten) are diffused into an oxide layer and react chemically with another element. This presents several problems. For example, the property of a semiconductor element is degraded. Further, unwanted film peeling occurs. To cope with these problems, a polysilicon layer is intervened between a dielectric layer and a metallic silicide film for isolation.
FIG. 16 is an example showing in cross section a first conventional MOS semiconductor device employing a metallic silicide film. A gate dielectric layer 2 (5 to 16 nm thick) formed by silicon dioxide (SiO.sub.2)) is grown on a silicon substrate 1 by means of oxidation. A polysilicon layer 3 (50 to 200 nm thick) is formed on top of the gate dielectric layer 2. Then, the polysilicon layer 3 is subjected to an ion implantation with gate impurities (for example, arsenic ions) at an implantation energy of 40 keV at a dose of 4 to 8.times.10.sub.15 cm.sup.-3. A tungsten silicide (WSix) film 4 (50 to 200 nm thick) is deposited on the polysilicon layer 3. Then, a silicon oxide layer 5 (50 to 200 nm thick), formed by silicon dioxide (SiO.sub.2), is formed by means of a chemical vapor deposition (CVD) process. After the step of transferring patterns is completed, the polysilicon layer 3, the WSix film 4, and the silicon oxide layer 5 are etched sequentially, thereby forming a gate electrode. Further, at a later step, a heat treatment is carried out at 850.degree. to 950.degree. C. for the activation of the impurities, the crystallization of the WSix film 4, and the planarization of the interlevel layer.
If the gate dielectric layer 2 directly contacts with the WSix film 4, the chemical reaction of tungsten with silicon dioxide occurs. This presents problems. For example, a gate-to-source (or gate-to-drain) leakage current occurs. Further, the reliability of gate dielectric layers falls. To overcome such problems, the polysilicon layer 3 doped with impurities is inserted between the WSix film 4 and the gate dielectric layer 2, and the polysilicon layer 3 and the WSix film 4 as one integral body constitute a gate electrode.
The effect of forming the silicon oxide layer 5 on the surface of the WSix film 4 gives several advantages. Without the provision of the silicon oxide layer 5 on the WSix film 4, the WSix film 5 will be oxidized immediately during a later heat treatment. This causes short between wires and between a source and a drain. Further, impurities to a gate are prevented at the time of another ion implantation.
Japanese Patent Application (Pub. No. 63-76479) attempts to prevent a tungsten silicide film from being oxidized by the deposition of a polysilicon layer (or an amorphous silicon layer) on the tungsten silicide film. This, however, leaves the polysilicon layer on the surface of the tungsten silicide film, requiring the provision of an electrical contact with a wire in the polysilicon layer. Due to the existence of an electrical contact, it may not be possible to make good use of an advantageous nature inherent in metallic silicides (i.e. a low resistivity). This is why a silicon oxide layer is deposited on the surface of a metallic silicide film.
The doping profiles, from the silicon oxide layer 5 towards the silicon substrate 1, of oxygen and arsenic (n-type impurities) are shown in FIG. 17. N-type impurities such as arsenic ions are likely to aggregate at the interface between an oxide layer and another different layer. As seen from FIG. 17, the arsenic concentration is high at the interface between the gate dielectric layer 2 and the polysilicon layer 3 as well as at the interface between the WSix film 4 and the silicon oxide layer 5.
FIG. 20 is similar to FIG. 16 but shows the doping profiles of oxygen and boron (p-type impurities) when boron ions are used as gate impurities. As shown in FIG. 20, the post-heat-treatment population of boron ions in the WSix film 4 and the post-heat-treatment population of boron ions in the polysilicon layer 3 differ from those of arsenic ions as shown in FIG. 16. In other words, boron aggregates at the interface between the WSix film 4 and the silicon oxide layer 5, and the boron concentration is low particularly in the polysilicon layer 3. This is explained as follows. Since there exists a great difference in heat shrinkage between the WSix film 4 and the silicon oxide layer 5, the interface between the WSix film 4 and the silicon oxide layer 5 is stressed intensively, and thus the structure of the WSix film 4 in the vicinity of the interface becomes disordered. Boron is likely to aggregate in such a structure-disordered zone. Further, compared to the WSix layer 4, the solid solubility of boron in the polysilicon layer 3 is small so that boron in the polysilicon layer 3 is dissolved into the WSix film 4. This results in the decrease of the boron concentration in the polysilicon layer 3. To sum up, boron is more likely to aggregate towards the interface in comparison with arsenic.
In this prior art technique, a WSix film is partly used as an gate electrode. However, a molybdenum silicide film or a titanium silicide film may be employed and formed by the same process as a WSix film.
FIG. 18 is an example showing in cross section a second conventional semiconductor device. After the deposition of the WSix film 4, a silicon nitride layer 6 (50 to 200 nm thick) is formed. In other words, the silicon nitride layer 6 replaces the silicon oxide layer 5 of the first conventional semiconductor device. The doping profiles, from the silicon nitride layer 6 to the silicon substrate 1, of nitrogen and arsenic are shown in FIG. 19. Like FIG. 17, the arsenic concentration is high at the interface between the gate dielectric layer 2 and the polysilicon layer 3 as well as at the interface between the WSix film 4 and the silicon nitride layer 6. Accordingly, the second conventional semiconductor device has the same tendency as the first conventional semiconductor device.
If a silicon oxide layer is formed on the surface of a metallic silicide film (for example, a WSix film), film peeling is likely to occur for the following reasons.
(1) The gate impurities, implanted into the WSix film 4 at the forgoing step, are diffused into the vicinity of the interface between the WSix film 4 and the silicon oxide layer 5, and aggregate there, during a later heat treatment. Because of this aggregation of the gate impurities, tungsten in the WSix film 4 is unlikely to react chemically with silicon in the silicon oxide layer 5. This results in poor adhesion between these two layers, and peeling is likely to occur. To avoid such unwanted peeling, it is necessary to limit the dose of gate impurity. If the dose of gate impurity is limited, however, a gate becomes depleted and characteristics are degraded for the case of a MOS semiconductor device. The boron concentration in the polysilicon layer 3 particularly decreases if p-type gate impurities are used, so that, for the case of p-channel MOS semiconductor devices of a surface channel type, gate depletion particularly becomes serious.
(2) If an implantation of gate impurities is carried out directly from above the WSix film 4, this roughens the surface of the WSix film 4, leaving such a roughened surface exposed. Consequently, this leads to abnormal oxidization at a later heat treatment or oxidization step.
The same problems also arise when using a molybdenum silicide layer or titanium silicide layer and when using a silicon nitride layer.